Communications buses have many applications, for example, in transferring digital data within computers and integrated circuits. A communications bus can have many features, however, one of its most important features is that it provides a shared communication link. Such a shared communication link can allow for two units to communicate, such as a processor and memory of a computer, or can allow for many thousands of units to communication, such as many interconnected computers on the Internet. In this way, a communication link is a fundamental unit for composing large complex systems that must communicate with each other. A communication bus also provides for versatility of a system. A properly configured bus can provide for the easy addition or subtraction of units on the bus. Also, a communication bus provides for a low cost communication system. By dedicating a predetermined set of shared wires to use as a communication bus, many units that need to communicate with each other do not themselves need to dedicate other sets of wires amongst all the various units.
Although a communications bus provides advantages, there are limits. A communications bus has an associated maximum bandwidth for communicating information. Also, a communications bus cannot be simultaneously shared with all the units on the bus. Thus, communications bottlenecks can occur where the units on the bus compete for access to the bus. The maximum speed of a bus can be limited by such factors as the length of the bus, the number of units on the bus, and the need to support a range of devices. The configuration of a bus can be complicated by the range of devices with greatly different characteristics such as varying latencies, that is the time required to respond to a command, and varying data transfer rates. When the transmission rate of a unit is faster than the transfer rate of the bus, the bus may need to moderate how data is placed on the bus. Also, when the receive rate is slower than the transfer rate of the bus, the bus may again need to moderate how data is placed on the bus.
Prior art synchronous communications buses also suffer in performance because the operation of an initiator unit and a target unit are necessarily closely coupled. The initiator unit needs to continually have an indication of certain of the target units operations. Similarly, the target unit needs to continually have an indication of certain of the initiator units operations. While this provides for a closely controlled communications bus, it also introduces much lag, in particular, round-trip lag. For example, in executing a write operation, signals need to be generated by an initiator, directed to the target, processed by the target, a different signal needs to be generated by the target, the new signal is then directed to the initiator to initiate the desired write operation. In a sense, signals need to loop from the initiator, to the target, and back to the initiator. A read operation introduces a second round trip delay that also needs to be negotiated. Other aspects of the prior art will be discussed in conjunction with the description of the present invention below. To fully understand the present invention, it is very useful to first understand certain aspects of the prior art. Accordingly, the prior art is first reviewed; thereafter, embodiments of the present invention are described. With a full understanding of the prior art, the broad application of the present invention can be better appreciated. Moreover, one of skill in the art will understand the applicability of the present invention beyond the embodiments described herein.
General aspects of a communications bus can be understood with reference to FIG. 1. Shown in FIG. 1 is the organization of a communications bus 102. Communications bus 102 includes a first set of wires dedicated as control lines 104 and a second set of wires dedicated as data lines 106. Control lines 104 control the flow of information on communications bus 102 and in particular data on data lines 106. Among other things, information on control line 104 can indicate what type of information is on data lines 106. Information on control line 104 can further indicate the direction of the flow of information on data lines 106 including the source and destination of information. Data lines 106 carry information between a source and a destination. Such information can include an address indicating the destination of the data. Moreover, information on data lines 106 can carry complex commands to be received and processed by a destination unit.
When communicating or exchanging information, a bus transaction occurs. Generally, a bus transaction includes a request that issues a command, and an action that includes transferring the data. Shown in FIG. 2 is a block diagram of a communications system 200 that includes a bus master 202 a communications bus 204 and a bus slave 206. Bus master 202 is the unit that initiates a bus transaction by issuing a command and/or an address to be communicated over bus 204 and to be received by bus slave 206. After receipt of such command and/or address and when it is prepared to respond to the command and/or address, bus slave 206 responds by sending data to the master if the master had asked for data. In this manner, bus master 202 can read data from bus slave 206, that is, bus slave 206 transmits read data over communications bus 204. Bus slave 206 can also respond by receiving data from bus master 202 if bus master 202 had indicated a write operation. In this manner, bus master 202 can write data to bus slave 206 by transmitting information over communications bus 204.
There are various types of buses including processor/memory buses, backplane buses, input/output buses, and inter-block buses, including buses between blocks in an integrated circuit. Shown in FIG. 3A is a block diagram of computer system 300 that makes use of processor/memory bus 302, backplane bus 304 and I/O buses 306A and 306B. As shown, processor/memory bus 302 is a high speed bus for communicating information between processor 308 and memory 310. Because I/O devices 312 through 318 may also need to access processor 308 or memory 310, backplane bus 304 and I/O buses 306A and 306B are also provided in conjunction with bus adaptors 320A, 320B and 320C. Bus adaptor 320A is provided as an interface between processor/memory bus 302 and backplane bus 304. Bus adaptor 320A provides any necessary conversion between processor/memory bus 302 and backplane bus 304. Similarly, bus adaptors 320B and 320C provide any necessary conversion between backplane bus 304 and I/O buses 306A and 306B, respectively. By decoupling backplane bus 304 and I/O buses 306A and 306B, loading on processor memory bus 302 is greatly reduced. Shown in FIG. 3B is a block diagram of an integrated circuit 350 having various blocks 352A through 352D that are communicatively coupled to inter-block bus 354. Just as communications buses can be provided externally to an integrated circuit, inter-block bus 354 provides for bused communications within an integrated circuit 350. Although the scale may be different, the fundamental purpose of all these buses is the same-to communicate information from a source to a destination.
When communicating data, in general, or when communicating data on a communications bus, in particular, there necessarily has to be a transmitter of information and a receiver of information. In certain contexts, the transmitter and receiver can also be referred to as a source of information and a destination of information. Also, when discussing communications buses, master and slave units are sometimes used, where the slave unit is subservient to the master unit. The slave unit performs the actions requested by the master unit. In many situations, these roles are never changed; that is, a master unit is always a master unit and a slave unit is always a slave unit. In other configurations, however, units may be interchangeably masters or slaves. In such configurations, it is more convenient to refer to an initiator unit and a target unit. An initiator unit is therefore similar to a master-type unit in that it directs another unit to perform certain actions. An initiator unit may have the further functionality that it may operate as a slave-type unit in another situation. Because the present invention has wide applicability, the terms initiator and target units will be used, however, one of skill in the art will understand the present disclosures applicability to master and slave unit configurations and source and destination configurations.
In a communications bus configuration where there are multiple potential initiator units, there is a need for bus arbitration to control bus accesses; an arbiter unit performs this function. A bus transaction, therefore, includes steps for performing arbitration, requests, and executing the requested action. An initiator unit requiring use of a communications bus asserts a bus request but cannot use the bus unit until its bus request is granted by the arbiter. When granted access to the bus, the initiator unit proceeds to use the communications bus as necessary. Also, the initiator unit must signal to the arbiter unit that it is finished using the communications bus. The arbiter unit can then grant access to other initiator units as necessary. Many arbitration schemes are widely known in the art and include, for example, daisy chain arbitration, centralized parallel arbitration, and distributed arbitration.
With a general understanding of a communications bus, we now turn to protocols used in a communications bus. Shown in FIG. 4A is timing diagram 400 illustrating a prior art synchronous bus transfer protocol for writing information from an initiator unit to a target unit. Because it is a synchronous protocol, the initiator unit and the target unit operate based on a synchronized master clock 402. Note that in the proceeding discussion, any logic diagrams or logic devices are described as active-low logic level devices. One of skill in the art will understand, however, that active-high devices can also be used. In a situation where an initiator unit writes data to a target unit, the initiator unit prepares the write data WR_DATA 404 and the write address WR_ADDR 406. When such information is ready, shown as Addr0 and Data0 at time t0 408, the initiator unit provides a bus write request WR_REQ_B 410 as an active-low signal. At the next clock cycle, shown as t1 415, the target unit receives WR_REQ_B 410 and processes such request. When the target is ready to receive address and data information, the target unit activates a bus grant GNT_B 412 at time t2 414. At the next master clock cycle, shown as time t3 416, the first address Addr0 and the first data data0 are written to the target. Note that Addr0 and Data0 are depicted as being written at some small time after t3 416. This is done to illustrate any lag in processing or propagation through logic circuits. Such a lag can become quite significant when there are small clock cycles or where the propagation delay is long. Indeed, where such a lag exceeds the period of one clock cycle, a communications bus can exhibit significant errors that affects its operation or the operation of the communicatively coupled devices.
After Addr0 and Data0 are processed, subsequent address and data information, such as Addr1 through Addr3 and Data1 through Data3, can similarly be transmitted (for example, at times t5 420, t7 424, and t4 418). After a write request is complete, an initiator unit de-asserts bus write request WR_REQ_B 410 a short time after time t4 418; this short time is associated with a lag in processing or propagation through combinational logic. The target unit then responds by de-asserting the bus grant GNT_B 412. The bus is then made available for other use.
It should be noted that when receiving data, the target unit may periodically remove the bus grant signal to slow its receipt of information. In this way, the target unit can process any received information, prior to receiving more information. For example, at time t5 420, the target unit removes bus grant signal GNT_B 412 such that Addr2 and Data2 are not received by the target unit at time t6 422, but are instead received at time t7 424 after the bus grant signal GNT_B 412 is re-activated.
Shown in FIG. 4B is timing diagram 450 illustrating a prior art synchronous protocol for an initiator reading information from a target unit. Because it is a synchronous protocol, the initiator unit and the target unit operate based on master clock 452. In a situation where an initiator unit reads data from a target unit, the initiator unit first prepares the read address RD_ADDR 456. When such information is ready, shown as Addr0 at time t0 458, the initiator unit activates a bus read request RD_REQ_B 460. Sometime thereafter (note that lags are again illustrated for similar reasons as with FIG. 4B), at time t1 463, the target unit receives RD_REQ_B 460 and processes the request. When the target unit is ready to receive address information, the target unit asserts a bus grant GNT_B 462 at time t2 464. At the next clock 452 cycle, shown as time t3 466, the first address Addr0 is received by the target; the target unit can also receive subsequent address information such as Addr1 through Addr3. It should be noted that when reading address information, the target unit may periodically remove the bus grant GNT_B 462 signal to throttle when it reads address information from the initiator unit. In this way, the target unit signals the initiator unit when to provide the next item of address information. For example, at time t8 482, GNT_B 454 is de-activated thereby preventing the next address, Addr2, from being read. At time t5 472, however, GNT_B 454 is re-activated thereby indicating that Addr2 can be read. With regard to data that is to be read by the initiator, the target unit must first process and retrieve such data. For example, the target unit must process and retrieve Data0 associated with Addr0 and similarly, for other addresses. A read operation can take several clock cycles depending on whether any page breaks are required in a memory being accessed and also depending on the lag of a system. When RD_DATA 474 contains at least the first data to be read (i.e., Data0 at time t4 468), the target unit responsively asserts a read data ready signal RD_DATA_RDY_B 470. Data0 is placed on the bus at the next clock cycle, time t5 472. Subsequent read data information, such as Data1 through Data3, is similarly transmitted.
After a read request is complete, that is, when a target has received all the read address information, an initiator unit can de-assert bus read request RD_REQ_B 460 at time t6 472. The target unit then responds by de-asserting the bus grant GNT_B 454. When the target unit has completed providing all the read data information (i.e., Data0 through Data3) at time t9 784, it signals the initiator unit by asserting RD_DATA_RDY_B 470. The bus is then made available for other use. It should be noted that when reading data, the target unit may periodically remove the read data ready signal, RD_DATA_RDY_B signal 470 to throttle when it provides read information to the initiator unit. In this way, the target unit signals the initiator unit when information is being placed on the bus. For example, at time t6 478, RD_DATA_RDY_B 470 is de-asserted thereby preventing the next data, Data1, from being read. At time t7 480, however, RD_DATA_RDY_B 470 is re-asserted thereby indicating that Data1 can be read. In a situation where the communications bus stalls, a stall signal STALL_RD_DATA_B 476 is asserted thereby indicating that further data cannot be read. For example, at time t8 482, STALL_RD_DATA_B 476 is asserted such that Data2 is not placed on the communications bus. At time t9 484, however, where STALL_RD_DATA_B 476 is de-asserted, the next data, Data 2, is placed on the communications bus.
The bus transfer protocol illustrated in FIGS. 4A and 4B can be implemented in many different forms. Shown in FIG. 5 is an exemplary block diagram of communication system 500 that implements the protocol of FIGS. 4A and 4B. FIG. 5 depicts various components contained within initiator unit 502 and target unit 504 where the various blocks in communication bus 500 can be implemented as combinational logic or in other forms known in the art. As shown, initiator unit 502 is communicatively coupled to target unit 504 through communications bus 506. Within initiator unit 502 is Initiator Handshake State Machine 508 that receives signals 510 from within initiator unit 502 to determine whether a write or read operation over communications bus 506 will be necessary. If so, request generating unit 512 generates signal 514 as a logic level low WR_REQ_B or RD_REQ_B signal indicating a write request or a read request, respectively. Signal 514 is coupled to communications bus 506 and directed to target unit 504. Target unit 504 receives and processes request signal 514 at Target Handshaking State Machine 516. Responsive to signals 518 internal to target unit 504, Target Handshake State Machine 516 determines if or when it is available to process the initiator unit's request. If target unit 504 is available, Request Generating unit 520 generates signal 522 as a logic level low signal indicating that it is available. Signal 522 is directed to OR gate 524; OR gate 524 also receives request signal 514. Accordingly, both signal 514 and signal 522 must be a logic level low for the output signal of OR gate 524 to be a logic level low (recall, active level low devices are in use); the output of OR gate 524 is therefore grant bus request GNT_B signal 526. GNT_B signal 526 is directed to Initiator Handshake State Machine 508 and Initiator Request Generating Unit 510 to update such units on the status of communications bus 506. GNT_B signal 526 is then directed to Address Unit 526 and Address Unit 526 and Write Unit 527. More particularly, GNT_B signal 526 is directed to multiplexer 528 of Address Unit 526 and multiplexer 529 of Write Unit 527. Address Unit 526 is used for addressing functions in both write and read operations. Write Unit 527 is used for writing data from initiator unit 502 to target unit 504 over communications bus 506.
Prior to having received GNT_B signal 526, Address Unit 526 makes available a first Address at ADDR signal 530 by means of Address/Counter 534 and multiplexer 528. ADDR signal 530 can be a write address or a read address. Through the operation of multiplexer 528 and D Flip-Flop 532, the first address is continually written and re-written at every clock cycle to signal line 530 while GNT_B signal 526 is at logic level high. When GNT_B signal 526 becomes an active logic level low, target unit 504 receives the first address at ADDR signal 530. Subsequently and responsive to ADDR signal 530, Address/Counter 534 provides further address information through Multiplexer 528, through D Flip-Flop 532 and to ADDR signal 530. Target unit 504 can then receive further address information. Address/Counter Unit 534 receives signals 536 from within initiator unit 502 to determine appropriate address. Importantly, Address Unit 526 operates similarly for write and read operations.
In a write operation, Write Unit 527 is utilized. Prior to receiving an active level low GNT_B signal 526, Write Unit 527 makes available the first write data at WR_DATA signal 538. Through the operation of Multiplexer 529 and D Flip-Flop 540, the first write data was continually written and re-written at every clock cycle to WR_DATA signal 538 while GNT_B signal 526 was at logic level high (i.e., not active). When GNT_B signal 526 becomes logic level low (i.e., active), target unit 504 receives the first data at WR_DATA signal 538. Subsequently and responsive to WR_DATA signal 538, Write Data FIFO 544/FIFO Controller 546 provides further data through multiplexer 529, through D Flip-Flop 540 and to WR_DATA 538. Target Unit 504 can then receive further data corresponding to the received address information as discussed above. Write Data FIFO 544 is also coupled to signal lines 546 to receive appropriate data information from within initiator unit 502.
In a read operation, Read Unit 548 is utilized. Target unit 504, and in particular Read Unit 548, must have available at least the first addressed data (i.e., Data0), where the corresponding address (i.e., Addr0) was transmitted in the manner described with reference to Address Unit 526. With the first address information, Read Unit 548 can retrieve such addressed information, for example, from a memory, and provide it to Data FIFO 550 through signals 574. Multiplexer 552 operates similarly to the Multiplexers 528 and 529; and D Flip-Flop 554 operates similarly to D Flip-Flops 532 and 540 previously described. With Next_Data signal 556 at a logic level low and with the first read data available at Data FIFO 550, the first read data is continually provided at Read Data signal line 558. When FIFO Control and Data Output Control Unit 560 determines that target unit 504 is ready to provide the requested read data, FIFO Control and Data Output Control Unit 560 responsively provides Next_Data signal 556 to Multiplexer 552 and RD_DATA_RDY_B signal 564 to Initiator Unit 502, and in particular, FIFO Control and Data Latch Control Unit 566. With Next_Data signal 556 at a logic level low, the second and subsequent data is passed from Data FIFO 550, through Multiplexer 552, through D Flip-Flop 554, to Initiator Unit 502, and in particular Read Data FIFO 568. When at Read Data FIFO 568, read data can be distributed to initiator unit 502 through signal 570. FIFO Control and Data Latch Control Unit 566 provides further functionality by generating a bus read stall STALL_RD_DATA_B signal 572 to target unit 504, and in particular, FIFO Control and Data Output Control Unit 560. With such a STALL_RD_DATA_B signal 572 active, FIFO Control and Data Output Control Unit 560 makes NEXT_DATA signal 562 logic level high so as to throttle the data being passed through communications bus 506.
The prior art communications bus described with reference to FIGS. 4A, 4B and 5 suffers from certain disadvantages. For example, such a prior art system necessarily couples the operation of the initiator and target units. The initiator unit needs to continually have an indication of certain of the target units' operations. Similarly, the target unit needs to continually have an indication of certain of the initiator units operations. While this provides for a closely controlled communications bus, it also introduces much lag, in particular, round-trip lag. For example, in executing a write operation, signals needs to be generated by an initiator, directed to the target, processed by the target, a different signal needs to be generated by the target, the new signal is then directed to the initiator to initiate the desired write operation. In a sense, signals need to loop from the initiator, to the target, and back to the initiator. A read operation introduces a second round trip delay that also needs to be negotiated.
A further disadvantage is that a request signal (i.e., RD_REQ_B or WR_REQ_B) and a grant signal (i.e., GNT_B) have to be activated in a same clock cycle, which potentially causes read or write failures due to the roundtrip lag discussed above. Moreover, the grant signal from the target unit controls many logic functions within the initiator unit, but the processing of the grant signal at the initiator unit needs to be moderated so as to avoid long propagation delays. This, however, may not allow for proper or complete processing of the grant command. For example, a complex, but desirable feature at the initiator unit may need to be avoided because it cannot be processed in a short enough time.
Another problem with the prior art is that addresses have to be incremented at every clock cycle. But when the clock frequency is very high, processing of the address count cannot be completed in one clock cycle. A very high clock frequency can cause other problems both within the initiator unit and the target unit as certain processing may not be accomplished in one clock cycle. When this occurs, the wrong data may be present at the next clock frequency, thus causing an error condition.
The present invention, by decoupling the request and grant signals provides advantages over the prior art.